CD4029B Data Sheet, Product Informaon And Support

The CD4029B consists of a four-stage binary or BCD-decade up/down counter with provisions for look-ahead carry in both counting modes. The inputs consist of a single CLOCK, CARRY-IN (CLOCK ENABLE), BINARY/DECADE, UP/DOWN, PRESET ENABLE, and four individual JAN signals, Q1, Q2, Q3, Q4 and a CARRY OUT signal are provided as outputs. A high PRESET ENABLE signal allows information on the JAM INPUTS to preset the counter to any state asynchronously with the clock. A low on each JAM line, when the PRESET-ENABLE signal is high, resets the counter to its zero count. The counter is advanced one count at the positive transition of the clock when the CARRY-IN and PRESET ENALBE signals are low. The CARRY-OUT signal is normally high and goes low when the counter reaches its maximum count in the UP mode or the minimum count in the DOWN mode provided the CARRY-IN signal is low. The CARRY-IN signal in the low state can thus be considered a CLOCK ENABLE. The CARRY-IN terminal must be connected to VSS when not in use. Ripple-clocking allows for longer clock input rise and fall times. Preset Enable and individual Jam inputs provided, Binary or decade up/down counting, 5-V, 10-V, and 15-V parametric ratings BCD outputs in decade mode, 100% tested for quiescent current at 20 V, Standardized, symmetrical output characteristics, Meets all requirements of JEDEC Tentative Standard No. 13B, Standard Specifications for Description of ’B’ Series CMOS Devices Applications: Programmable binary and decade counting/frequency synthesizers-BCD output Analog to digital and digital to analog conversion Up/Down binary counting Magnitude and sign generation Up/Down decade counting Difference counting